In considering the Viterbi algorithm, two aspects in particular must be considered: the ‘Metric Calculation’ and the ‘Viterbi decoder’ itself. The theory of both of these aspects, involving calculation of branch, node and path metrics between different trellis nodes, is well known and ubiquitously applied in the field of digital communications.
The main problem of the Viterbi algorithm lies in its arithmetical decoding complexity (thus leading to high power consumption, etc., which is a paramount consideration in battery-operated portable communication devices). A lot of research has been done with the aim of reducing complexity associated with the Viterbi algorithm.
However, this research has invariably not taken into account the needs of ‘broadband communications’ systems. In these systems account must be taken of the very high bit rates involved, which require adaptation of the Viterbi algorithm for efficient maximum-likelihood decoding.
Standard implementations of the Viterbi algorithm are distinctly sub-optimum for ‘Broadband Communication’ systems because:    1) In the Viterbi decoder the arithmetically most complex part is the “Addition-Compare-Select (ACS) Unit” which is re-used several times during each decoding step. The vast majority of existing solutions propose to implement this “Addition Compare Select Unit” once (e.g., on an application specific integrated circuit (ASIC)) and to re-use it each time it is needed. Of course, this slows down the decoding compared to a fully parallel implementation. In “Broadband Communications” systems, however, there is a very high bit-rate and the re-use of blocks is often impossible due to clock frequency restrictions. In other words, a fully parallel implementation is often required which allows the decoding of one bit per clock cycle. Sometimes a partly parallel implementation is sufficient, representing a trade-off between the two extremes.    2) The standard proposed metrics allow little or no opportunity for varying the layout or configuration of a fully (or partly) parallel ASIC implementation, and although some suggestion has been made to vary the standard metrics these variations are still undesirably complex and sub-optimal for use in broadband communications implementations.
A need therefore exists for a Viterbi decoder, unit therefor and method wherein the abovementioned disadvantage(s) may be alleviated.